esd 53 05f will semiconductor ltd. 1 revision 1. 6 , 2014 / 12/08 esd 5305f 4 - line s , un i - d irectional, l ow c apacitance trans ient voltage suppressors descriptions the esd530 5f is a low capacitance tvs (transient voltage suppressor) array designed to protect high speed data interfaces. it has been specifically designed to protect sensitive electronic components which are connected to data and transmission lines from over - stress caused by esd (e lectro s tatic d ischarge ) . the esd530 5f incorporates four pairs of low capacitance steering diodes plus a tvs diode. the esd530 5f m ay be used to provide esd protection up to 30k v (contact discharge ) according to iec61000 - 4 - 2 , and withstand peak pulse current up to 6a ( 8/20 s ) according to iec61000 - 4 - 5. the esd530 5f is available in sot 23- 6l package. standard products are pb - free and h alogen - free. features ? reverse s tand - off voltage: 5 v m ax . ? transient protection for each line according to iec61000 - 4 - 2 (esd) : 30k v ( contact discharge ) iec61000 - 4 - 5 (surge): 6a (8/20 s) ? l ow capacitance: c i/o - gnd = 0.65 pf typ. (vcc = floated) c i/o - gnd = 0.35 pf typ. (vcc = 5v) ? ultra - low leakage current: i r < 1na typ. ? l ow clamping voltage : v cl = 1 6.5v @ i pp = 16a (tlp) ? solid - state silico n technology applications ? usb 2.0 ? hdmi 1.3 ? sata and esata ? dvi ? ieee 1394 ? pci express ? portable electronics ? notebooks h ttp //: www. sh - willsemi.com sot 23- 6l circuit d iagram 5305 = device code yy = year code ww = week code marking & pin configuration (top view) order i nformation device package shipping esd 530 5f - 6 /tr sot 23- 6l 3 000/tape&reel 1 3 4 6 2 5 6 4 5 3 1 2 i/o i/o vcc i/o i/o gnd 5305 yyww
esd 53 05f will semiconductor ltd. 2 revision 1. 6 , 2014 / 12/08 absolute m aximum r ating s electrical characteristics ( t a = 25 o c , unless otherwise noted ) definitions of electrical characteristics parameter symbol rating unit peak pulse power ( t p = 8/20 s) p pk 84 w peak pulse current (t p = 8/20 s) i pp 6 a esd according to iec61000 - 4 - 2 air discharge v esd 30 k v esd according to iec61000 - 4 - 2 contact discha rge 30 j unction t emperature t j 1 25 o c operating temperature t op - 40~ 85 o c lead temperature t l 260 o c storage temperature t stg - 55~150 o c i v v f v rwm v br v fc i pp i f i r i br v cl i pp v f forward voltage i f forward current v fc forward clamping voltage i pp peak pulse current v rwm reverse stand-off voltage i r reverse leakage current v br reverse breakdown voltage v cl clamping voltage i pp peak pulse current
esd 53 05f will semiconductor ltd. 3 revision 1. 6 , 2014 / 12/08 elect rical characteristics ( t a = 25 o c , unless otherwise noted ) notes: 1) tlp parameter: z 0 = 50 , t p = 100ns, t r = 2n s, averaging window fr om 60ns to 80ns. r dyn is calculated from 4a to 16a. 2) non - repetitive current pulse, according to iec61000-4 -5. parameter symbol condition min. typ. max. unit reverse stand - off voltage v rwm 5.0 v rever se leakage current i r v rwm = 5 v < 1 5 0 n a rever se breakdown voltage v br i br = 1ma 7.0 8. 0 9.0 v forwar d voltage v f i f = 1 0ma 0.6 0. 9 1.2 v clamping voltage 1) v cl i pp = 16a, t p = 100ns 1 6.5 v dynamic resistance 1) r dyn 0. 4 5 2 ) v cl i pp = 1a, t p = 8/20s = 8/20s
esd 53 05f will semiconductor ltd. 4 revision 1. 6 , 2014 / 12/08 typical characteristics ( t a = 25 o c , unless otherwise noted ) 8/20 s w aveform per iec61000 - 4 - 5 clamping voltage vs. peak pulse current non - repetitive peak pulse p ower vs. pulse time contact discharge current waveform per iec61000 - 4 - 2 capacitance vs. rever se voltage power derating vs. ambient t emperature 0 1 2 3 4 5 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i/o to i/o vcc = floated, i/o to gnd vcc = 5v, i/o to gnd f = 1mhz junction capacitance (pf) v r - reverse voltage (v) 0 25 50 75 100 125 150 0 20 40 60 80 100 % of rated power t a - ambient temperature ( o c) 0 1 2 3 4 5 6 7 9 10 11 12 13 14 pulse waveform: t p = 8/20
esd 53 05f will semiconductor ltd. 5 revision 1. 6 , 2014 / 12/08 typical characteristics ( t a = 25 o c , unless otherwise noted ) esd clamping ( +8kv contact discharge per iec61000 - 4 - 2) tlp measurement esd clamping ( - 8kv contact discharge per iec 61000 - 4 - 2 ) -2 0 2 4 6 8 10 12 14 16 18 20 -2 0 2 4 6 8 10 12 14 16 18 20 22 z 0 = 50 ? t r = 2ns t p = 100ns tlp current (a) tlp voltage (v)
esd 53 05f will semiconductor ltd. 6 revision 1. 6 , 2014 / 12/08 package outline dimensions sot 23- 6 l recommended l and pattern (unit: mm ) symbol dimensions in millimeters min. typ. max. a -- -- 1.25 a1 0 -- 0.1 5 a2 1.0 0 1.10 1.20 a3 0.60 0.65 0.70 b 0.36 -- 0.50 b1 0.36 0.38 0.45 c 0.14 -- 0.20 c1 0.14 0.15 0.16 d 2.826 2.926 3.026 e 2 . 60 2.80 3.00 e1 1.526 1.626 1.726 e 0.90 0.95 1.00 e 1 1.80 1.90 2.00 l 0.35 0.45 0.60 l1 0.59ref l2 0.25bsc r 0.10 -- -- r1 0.10 -- 0.20 0 o -- 8 o 1 3 o 5 o 7 o 2 6 o -- 14 o 1.10 0.95 3.60 1.40 2.50 0.60 note s : t his recommended land pattern is for reference purposes only. p lease consult your manufacturing group to ensure your pcb design guidelines are met.
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